Jesd204bTxWrapper Entity Reference

Inheritance diagram for Jesd204bTxWrapper:

Collaboration diagram for Jesd204bTxWrapper:

Entities
Jesd204bTxWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
F_G	positive := 2
K_G	positive := 32
L_G	positive range 1 to 16 := 2
DID_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
BID_G	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
M_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
N_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
NPRIME_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
CS_G	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
S_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
HD_G	sl := ' 0 '
CF_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
ADDR_WIDTH	positive := 12

Ports
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S_AXI_AWADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_AWVALID	in	std_logic
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_WVALID	in	std_logic
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic
S_AXI_ARADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_ARVALID	in	std_logic
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic
devClk_i	in	sl
devRst_i	in	sl
sysRef_i	in	sl
nSync_0_i	in	sl
nSync_1_i	in	sl
extData_0_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
extData_1_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtTxReady_0_i	in	sl
gtTxReady_1_i	in	sl
gtTxData_0_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtTxDataK_0_o	out	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtTxData_1_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtTxDataK_1_o	out	slv ( GT_WORD_SIZE_C- 1 downto 0 )
txDiffCtrl_0_o	out	slv ( 7 downto 0 )
txPolarity_0_o	out	slv ( 0 downto 0 )
loopback_0_o	out	slv ( 0 downto 0 )
dacReady_0_o	out	sl
dacReady_1_o	out	sl

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The documentation for this design unit was generated from the following file:

• protocols/jesd204b/wrappers/Jesd204bTxWrapper.vhd