Architecture >> Jesd204bTb::tb

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
rstL	sl := ' 1 '
configDone	sl := ' 0 '
sysRef	sl := ' 0 '
nSync	sl := ' 0 '
jesdGtTxArr	jesdGtTxLaneType := JESD_GT_TX_LANE_INIT_C
jesdGtRxArr	jesdGtRxLaneType := JESD_GT_RX_LANE_INIT_C
txReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
txReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
txWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
txWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
rxReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
rxReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
rxWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
rxWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
txData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
rxValid	sl := ' 0 '
rxData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
nextRxData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt	slv ( 6 downto 0 ) := ( others = > ' 0 ' )
rxDataErrorDet	sl := ' 0 '
data	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
dataK	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
kCharDet	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
rCharDet	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
aCharDet	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
fCharDet	slv ( 3 downto 0 ) := ( others = > ' 0 ' )

The documentation for this design unit was generated from the following files:

Processes

Constants