Iprog7Series.rtl Architecture Reference

Architecture >> Iprog7Series::rtl

Signals
icapClk	sl
icapClkRst	sl
icapCsl	sl
icapRnw	sl
icapI	slv ( 31 downto 0 )

Instantiations
bufr_icpape2	bufr
rstsync_inst	RstSync <Entity RstSync>
iprog7seriescore_1	Iprog7SeriesCore <Entity Iprog7SeriesCore>
icape2_inst	icape2

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Iprog7Series.vhd