Iprog7Series Entity Reference

Inheritance diagram for Iprog7Series:

Collaboration diagram for Iprog7Series:

Entities
Iprog7Series.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
USE_SLOWCLK_G	boolean := false
BUFR_CLK_DIV_G	string := " 8 "

Ports
clk	in	sl
rst	in	sl
slowClk	in	sl := ' 0 '
start	in	sl
bootAddress	in	slv ( 31 downto 0 ) := X " 00000000 "

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Iprog7Series.vhd