Iprog7SeriesCore Entity Reference

Inheritance diagram for Iprog7SeriesCore:

Collaboration diagram for Iprog7SeriesCore:

Entities
Iprog7SeriesCore.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SYNC_RELOAD_G	boolean := true

Ports
reload	in	sl
reloadAddr	in	slv ( 31 downto 0 ) := X " 00000000 "
icapClk	in	sl
icapClkRst	in	sl
icapReq	out	sl
icapGrant	in	sl := ' 1 '
icapCsl	out	sl
icapRnw	out	sl
icapI	out	slv ( 31 downto 0 )

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd