Iprog7SeriesCore.rtl Architecture Reference

Architecture >> Iprog7SeriesCore::rtl

Functions
slv	selectMapBitSwapping ( input: in slv )

Processes
comb	( icapClkRst , icapGrant , icapReload , icapReloadAddr , r )
seq	( icapClk )

Constants
BYPASS_SYNC_C	boolean := not SYNC_RELOAD_G
REG_INIT_C	RegType := ( state = > IDLE_S , req = > ' 0 ' , csl = > ' 1 ' , rnw = > ' 1 ' , cnt = > ( others = > ' 0 ' ) , configData = > ( others = > ' 0 ' ) )

Types
StateType	( IDLE_S , REQ_S , PROG_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
icapReloadAddr	slv ( 31 downto 0 )
icapReload	sl

Records
RegType

Instantiations
synchronizeraddress_1	SynchronizerVector <Entity SynchronizerVector>
synchronizerstart_1	SynchronizerEdge <Entity SynchronizerEdge>

---

The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd