IpV4EngineRx.rtl Architecture Reference

Architecture >> IpV4EngineRx::rtl

Processes
comb	( r , rst , rxMaster , txSlave )
seq	( clk )

Constants
REG_INIT_C	RegType := ( tLast = > ' 0 ' , eofe = > ' 0 ' , len = > ( others = > ' 0 ' ) , protocol = > ( others = > ' 0 ' ) , tKeep = > ( others = > ' 0 ' ) , tData = > ( others = > ' 0 ' ) , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , IPV4_HDR0_S , IPV4_HDR1_S , IPV4_HDR2_S , MOVE_S , LAST_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxMaster	AxiStreamMasterType
rxSlave	AxiStreamSlaveType
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_mux	AxiStreamMux <Entity AxiStreamMux>
u_axismux	AxiStreamDeMux <Entity AxiStreamDeMux>

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The documentation for this design unit was generated from the following file:

• ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd