IpV4EngineRx Entity Reference

Inheritance diagram for IpV4EngineRx:

Collaboration diagram for IpV4EngineRx:

Entities
IpV4EngineRx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SIM_ERROR_HALT_G	boolean := false
PROTOCOL_SIZE_G	positive := 1
PROTOCOL_G	Slv8Array := ( 0 = > UDP_C )

Ports
ibIpv4Master	in	AxiStreamMasterType
ibIpv4Slave	out	AxiStreamSlaveType
localhostMaster	in	AxiStreamMasterType
localhostSlave	out	AxiStreamSlaveType
ibProtocolMasters	out	AxiStreamMasterArray ( PROTOCOL_SIZE_G- 1 downto 0 )
ibProtocolSlaves	in	AxiStreamSlaveArray ( PROTOCOL_SIZE_G- 1 downto 0 )
clk	in	sl
rst	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd