GigEthLvdsUltraScale.mapping Architecture Reference

Architecture >> GigEthLvdsUltraScale::mapping

Components
GigEthLvdsUltraScaleCore

Signals
config	GigEthConfigType
status	GigEthStatusType
mAxiReadMaster	AxiLiteReadMasterType
mAxiReadSlave	AxiLiteReadSlaveType
mAxiWriteMaster	AxiLiteWriteMasterType
mAxiWriteSlave	AxiLiteWriteSlaveType
gmiiTxd	slv ( 7 downto 0 )
gmiiTxEn	sl
gmiiTxEr	sl
gmiiRxd	slv ( 7 downto 0 )
gmiiRxDv	sl
gmiiRxEr	sl
sysClk125En	sl
sysClk125	sl
sysRst125	sl
areset	sl

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_mac	EthMacTop <Entity EthMacTop>
u_gigethlvdsultrascalecore	gigethlvdsultrascalecore
u_gigethreg	GigEthReg <Entity GigEthReg>

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd