GigEthLvdsUltraScale Entity Reference

Inheritance diagram for GigEthLvdsUltraScale:

Collaboration diagram for GigEthLvdsUltraScale:

Entities
GigEthLvdsUltraScale.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
GigEthPkg	Package <GigEthPkg>

Generics
TPD_G	time := 1 ns
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
EN_AXIL_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
speed_is_10_100	in	sl := ' 0 '
speed_is_100	in	sl := ' 0 '
extRst	in	sl
ethClk	out	sl
ethRst	out	sl
phyReady	out	sl
sigDet	in	sl := ' 1 '
sgmiiClkP	in	sl
sgmiiClkN	in	sl
sgmiiTxP	out	sl
sgmiiTxN	out	sl
sgmiiRxP	in	sl
sgmiiRxN	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd