GigEthGthUltraScale.mapping Architecture Reference

Architecture >> GigEthGthUltraScale::mapping

Components
GigEthGthUltraScaleCore

Signals
config	GigEthConfigType
status	GigEthStatusType
mAxiReadMaster	AxiLiteReadMasterType
mAxiReadSlave	AxiLiteReadSlaveType
mAxiWriteMaster	AxiLiteWriteMasterType
mAxiWriteSlave	AxiLiteWriteSlaveType
gmiiTxClk	sl
gmiiTxd	slv ( 7 downto 0 )
gmiiTxEn	sl
gmiiTxEr	sl
gmiiRxClk	sl
gmiiRxd	slv ( 7 downto 0 )
gmiiRxDv	sl
gmiiRxEr	sl
areset	sl
coreRst	sl

Attributes
dont_touch	string
dont_touch	signal is " TRUE "

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_mac	EthMacTop <Entity EthMacTop>
u_gigethgthultrascalecore	gigethgthultrascalecore
u_gigethreg	GigEthReg <Entity GigEthReg>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_mac	EthMacTop <Entity EthMacTop>
u_gigethgthultrascalecore	gigethgthultrascalecore
u_gigethreg	GigEthReg <Entity GigEthReg>

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The documentation for this design unit was generated from the following files:

• ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd
• ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd