GigEthGthUltraScale Entity Reference

Inheritance diagram for GigEthGthUltraScale:

Collaboration diagram for GigEthGthUltraScale:

Entities
GigEthGthUltraScale.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
GigEthPkg	Package <GigEthPkg>

Generics
TPD_G	time := 1 ns
INT_PIPE_STAGES_G	natural := 1
PIPE_STAGES_G	natural := 1
FIFO_ADDR_WIDTH_G	positive := 12
SYNTH_MODE_G	string := " xpm "
MEMORY_TYPE_G	string := " ultra "
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
EN_AXI_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axiLiteClk	in	sl := ' 0 '
axiLiteRst	in	sl := ' 0 '
axiLiteReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave	out	AxiLiteReadSlaveType
axiLiteWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave	out	AxiLiteWriteSlaveType
sysClk62	in	sl
sysClk125	in	sl
sysRst125	in	sl
extRst	in	sl
phyReady	out	sl
sigDet	in	sl := ' 1 '
gtTxPolarity	in	sl := ' 0 '
gtRxPolarity	in	sl := ' 0 '
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl

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The documentation for this design unit was generated from the following files:

• ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd
• ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd