Architecture >> FirFilterSingleChannel::mapping

Functions
CoeffArray	initCoeffArray

Processes
comb	( axiWrAddr , axiWrData , axiWrValid , cascout , ibValid , obReady , r , rst , sbIn )
seq	( clk )

Constants
CASC_WIDTH_C	integer := COEFF_WIDTH_G+ DATA_WIDTH_G+ log2 ( NUM_TAPS_G )
COEFFICIENTS_C	CoeffArray := initCoeffArray
NUM_ADDR_BITS_C	positive := bitSize ( NUM_TAPS_G- 1 )
FILTER_DELAY_C	integer := ( NUM_TAPS_G- 1 ) / 2
REG_INIT_C	RegType := ( coeffin = > COEFFICIENTS_C , ibReady = > ' 0 ' , tdata = > ( others = > ' 0 ' ) , tValid = > ( others = > ' 0 ' ) , sideband = > ( others = > ( others = > ' 0 ' ) ) , readSlave = > AXI_LITE_READ_SLAVE_INIT_C , writeSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
CoeffArray	( NUM_TAPS_G- 1 downto 0 ) slv ( COEFF_WIDTH_G- 1 downto 0 )
CascArray	( NUM_TAPS_G- 1 downto 0 ) slv ( CASC_WIDTH_C- 1 downto 0 )
SidebandPipelineArray	( FILTER_DELAY_C- 1 downto 0 ) slv ( SIDEBAND_WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
cascin	CascArray
cascout	CascArray
cascTapEn	sl
axiWrValid	sl := ' 0 '
axiWrAddr	slv ( NUM_ADDR_BITS_C- 1 downto 0 ) := ( others = > ' 0 ' )
axiWrData	slv ( 31 downto 0 ) := ( others = > ' 0 ' )

Records
RegType

Instantiations
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_tap	FirFilterTap <Entity FirFilterTap>

The documentation for this design unit was generated from the following file:

Functions

Processes