FirFilterSingleChannel Entity Reference

Inheritance diagram for FirFilterSingleChannel:

Collaboration diagram for FirFilterSingleChannel:

Entities
FirFilterSingleChannel.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
NUM_TAPS_G	positive
SIDEBAND_WIDTH_G	positive := 1
IBREADY_DEFAULT_G	sl := ' 1 '
DATA_WIDTH_G	positive
COEFF_WIDTH_G	positive range 1 to 32
COEFFICIENTS_G	IntegerArray := ( 0 = > 0 )

Ports
clk	in	sl
rst	in	sl
ibValid	in	sl := ' 1 '
ibReady	out	sl
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
sbIn	in	slv ( SIDEBAND_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
obValid	out	sl
obReady	in	sl := ' 1 '
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
sbOut	out	slv ( SIDEBAND_WIDTH_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/FirFilterSingleChannel.vhd
• dsp/generic/fixed/FirFilterSingleChannel.vhd