DeviceDnaUltraScale.rtl Architecture Reference

Architecture >> DeviceDnaUltraScale::rtl

Processes
comb	( dnaDout , locRst , r )
sync	( locClk )

Constants
DNA_SHIFT_LENGTH_C	natural := 96
REG_INIT_C	RegType := ( state = > READ_S , bitCount = > 0 , dnaValue = > ( others = > ' 0 ' ) , dnaValid = > ' 0 ' , dnaRead = > ' 1 ' )

Types
StateType	( READ_S , SHIFT_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
dnaDout	sl
divClk	sl
locClk	sl
locRst	sl
dnaRead	sl

Records
RegType

Instantiations
bufgce_div_inst	bufgce_div
rstsync_inst	RstSync <Entity RstSync>
dna_port_i	dna_porte2
syncvalid	Synchronizer <Entity Synchronizer>
syncdata	SynchronizerVector <Entity SynchronizerVector>

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/DeviceDnaUltraScale.vhd