ClinkDataClk.rtl Architecture Reference

Architecture >> ClinkDataClk::rtl

Signals
clkInLoc	sl
clkOutMmcm	slv ( 1 downto 0 )
clkOutLoc	slv ( 1 downto 0 )
clkFbOut	sl
clkFbIn	sl
lockedLoc	sl
genReset	sl
drpRdy	sl
drpEn	sl
drpWe	sl
drpAddr	slv ( 6 downto 0 )
drpDi	slv ( 15 downto 0 )
drpDo	slv ( 15 downto 0 )

Instantiations
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
u_mmcm	mmcme2_adv
u_bufin	bufr
u_buffb	bufr
u_bufout	bufr
u_bufio	bufio
u_bufin	bufg
u_buffb	bufg
u_bufout	bufg
u_bufio	bufg
u_rstsync	RstSync <Entity RstSync>
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
u_mmcm	mmcme3_adv
u_bufin	bufg
u_buffb	bufg
u_bufout	bufg
u_bufio	bufg
u_bufin	bufg
u_buffb	bufg
u_bufout	bufg
u_bufio	bufg
u_rstsync	RstSync <Entity RstSync>

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The documentation for this design unit was generated from the following files:

• protocols/clink/7Series/ClinkDataClk.vhd
• protocols/clink/UltraScale/ClinkDataClk.vhd