AxiVersionIpIntegrator.mapping Architecture Reference

Architecture >> AxiVersionIpIntegrator::mapping

Processes
PROCESS_0	( userValues )
PROCESS_97	( userValues )

Constants
ADDR_WIDTH_C	positive := 12
CLK_PERIOD_C	real := ( 1 . 0 / real ( FREQ_HZ ) )

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType
userValuesArray	Slv32Array ( 0 to 63 )

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axiversion	AxiVersion <Entity AxiVersion>
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axiversion	AxiVersion <Entity AxiVersion>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd
• build/SRC_VHDL/surf/AxiVersionIpIntegrator.vhd