AxiVersionIpIntegrator Entity Reference

Inheritance diagram for AxiVersionIpIntegrator:

Collaboration diagram for AxiVersionIpIntegrator:

Entities
AxiVersionIpIntegrator.mapping	architecture

Libraries
ieee
surf
ruckus

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
BuildInfoPkg	Package <BuildInfoPkg>

Generics
EN_ERROR_RESP	boolean := false
FREQ_HZ	positive := 125000000

Ports
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S_AXI_AWADDR	in	std_logic_vector ( 11 downto 0 )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_AWVALID	in	std_logic
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_WVALID	in	std_logic
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic
S_AXI_ARADDR	in	std_logic_vector ( 11 downto 0 )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_ARVALID	in	std_logic
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic
userReset	out	std_logic
fpgaEnReload	in	std_logic := ' 1 '
fpgaReload	out	std_logic
fpgaReloadAddr	out	std_logic_vector ( 31 downto 0 )
upTimeCnt	out	std_logic_vector ( 31 downto 0 )
slowClk	in	std_logic := ' 0 '
dnaValueOut	out	std_logic_vector ( 127 downto 0 )
fdValueOut	out	std_logic_vector ( 63 downto 0 )
userValues	in	std_logic_vector ( ( 64 * 32 ) - 1 downto 0 ) := ( others = > ' 0 ' )
fdSerSdio	inout	std_logic := ' Z '

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd
• build/SRC_VHDL/surf/AxiVersionIpIntegrator.vhd