AxiStreamTimerIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamTimerIpIntegrator::rtl

Signals
axilResetN	sl := ' 1 '
streamMasters	AxiStreamMasterArray ( NUM_STREAMS_G- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
streamSlaves	AxiStreamSlaveArray ( NUM_STREAMS_G- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_shimlayerslave	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamTimer <Entity AxiStreamTimer>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd