AxiStreamTimerIpIntegrator Entity Reference

Inheritance diagram for AxiStreamTimerIpIntegrator:

Collaboration diagram for AxiStreamTimerIpIntegrator:

Entities
AxiStreamTimerIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
NUM_STREAMS_G	integer range 1 to 8 := 2
NUM_EVENT_G	integer range 1 to 16 := 2
DATA_BYTES_G	positive := 4

Ports
axisClk	in	sl
axisRst	in	sl
axilClk	in	sl
axilRst	in	sl
S0_AXIS_TVALID	in	sl := ' 0 '
S0_AXIS_TDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
S0_AXIS_TKEEP	in	slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S0_AXIS_TLAST	in	sl := ' 0 '
S0_AXIS_TREADY	in	sl := ' 0 '
S1_AXIS_TVALID	in	sl := ' 0 '
S1_AXIS_TDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
S1_AXIS_TKEEP	in	slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S1_AXIS_TLAST	in	sl := ' 0 '
S1_AXIS_TREADY	in	sl := ' 0 '
S_AXI_AWADDR	in	slv ( 31 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 31 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd