AxiStreamMuxIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamMuxIpIntegrator::rtl

Constants
PRIORITY_C	IntegerArray ( 1 downto 0 ) := ( 0 = > PRIORITY_0_G , 1 = > PRIORITY_1_G )
TDEST_ROUTES_C	Slv8Array ( 1 downto 0 ) := ( 0 = > toSlv ( TDEST_ROUTE_0_G , 8 ) , 1 = > toSlv ( TDEST_ROUTE_1_G , 8 ) )
TID_ROUTES_C	Slv8Array ( 1 downto 0 ) := ( 0 = > toSlv ( TID_ROUTE_0_G , 8 ) , 1 = > toSlv ( TID_ROUTE_1_G , 8 ) )

Signals
axisAResetN	sl := ' 1 '
sAxisMasters	AxiStreamMasterArray ( 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
sAxisSlaves	AxiStreamSlaveArray ( 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayerslave0	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayerslave1	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamMux <Entity AxiStreamMux>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd