Architecture >> AxiStreamMonAxiL::rtl

Processes
comb	( axisRst , bandwidth , bandwidthMax , bandwidthMin , frameCnt , frameRate , frameRateMax , frameRateMin , frameSize , frameSizeMax , frameSizeMin , r )
seq	( axisClk , axisRst )
comb	( axisRst , bandwidth , bandwidthMax , bandwidthMin , frameCnt , frameRate , frameRateMax , frameRateMin , frameSize , frameSizeMax , frameSizeMin , r )
seq	( axisClk , axisRst )

Constants
ADDR_WIDTH_C	*positive := bitSize ( AXIS_NUM_SLOTS_G 16 - 1 )**
REG_INIT_C	RegType := ( we = > ' 0 ' , data = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 1 ' ) , addr = > ( others = > ' 1 ' ) , ch = > 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
rstCnt	sl
localReset	sl
axisReset	sl
frameCnt	Slv64Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameSize	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameSizeMax	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameSizeMin	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameRate	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameRateMax	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
frameRateMin	Slv32Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
bandwidth	Slv64Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
bandwidthMax	Slv64Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )
bandwidthMin	Slv64Array ( AXIS_NUM_SLOTS_G- 1 downto 0 )

Records
RegType

Instantiations
u_rstsync	RstSync <Entity RstSync>
u_axistreammon	AxiStreamMon <Entity AxiStreamMon>
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>
u_rstsync	RstSync <Entity RstSync>
u_axistreammon	AxiStreamMon <Entity AxiStreamMon>
u_axidualportram	AxiDualPortRam <Entity AxiDualPortRam>

The documentation for this design unit was generated from the following files:

Processes

Constants