AxiStreamMonAxiL Entity Reference

Inheritance diagram for AxiStreamMonAxiL:

Collaboration diagram for AxiStreamMonAxiL:

Entities
AxiStreamMonAxiL.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
AXIS_CLK_FREQ_G	real := 156 . 25E + 6
AXIS_NUM_SLOTS_G	positive := 1
AXIS_CONFIG_G	AxiStreamConfigType

Ports
axisClk	in	sl
axisRst	in	sl
axisMasters	in	AxiStreamMasterArray ( AXIS_NUM_SLOTS_G- 1 downto 0 )
axisSlaves	in	AxiStreamSlaveArray ( AXIS_NUM_SLOTS_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType

---

The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamMonAxiL.vhd
• build/SRC_VHDL/surf/AxiStreamMonAxiL.vhd