AxiStreamMonAxiLIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamMonAxiLIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 1 , TID_BITS_C = > 1 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 1 , TUSER_MODE_C = > TUSER_NORMAL_C )

Signals
axisResetN	sl := ' 1 '
axilResetN	sl := ' 1 '
axisMasters	AxiStreamMasterArray ( 0 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
axisSlaves	AxiStreamSlaveArray ( 0 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_axis	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamMonAxiL <Entity AxiStreamMonAxiL>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd