Architecture >> AxiStreamDmaV2WriteIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > DATA_BYTES_G , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > DATA_BYTES_G , ID_BITS_C = > 8 , LEN_BITS_C = > 8 )

Signals
axisAResetN	sl := ' 1 '
dmaWrDescReq	AxiWriteDmaDescReqType := AXI_WRITE_DMA_DESC_REQ_INIT_C
dmaWrDescAck	AxiWriteDmaDescAckType := AXI_WRITE_DMA_DESC_ACK_INIT_C
dmaWrDescRet	AxiWriteDmaDescRetType := AXI_WRITE_DMA_DESC_RET_INIT_C
axisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiWriteCtrl	AxiCtrlType := AXI_CTRL_UNUSED_C

Instantiations
u_streamslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_axiwritemaster	MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut	AxiStreamDmaV2Write <Entity AxiStreamDmaV2Write>

The documentation for this design unit was generated from the following file:

Constants

Signals