AxiStreamDmaV2WriteIpIntegrator Entity Reference

Inheritance diagram for AxiStreamDmaV2WriteIpIntegrator:

Collaboration diagram for AxiStreamDmaV2WriteIpIntegrator:

Entities
AxiStreamDmaV2WriteIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
AXI_READY_EN_G	boolean := false
PIPE_STAGES_G	natural := 1
BURST_BYTES_G	integer range 1 to 4096 := 16
ACK_WAIT_BVALID_G	boolean := false
DATA_BYTES_G	positive := 4

Ports
axiClk	in	sl
axiRst	in	sl
dmaWrDescReqValid	out	sl
dmaWrDescReqId	out	slv ( 7 downto 0 )
dmaWrDescReqDest	out	slv ( 7 downto 0 )
dmaWrDescAckValid	in	sl := ' 0 '
dmaWrDescAckAddress	in	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
dmaWrDescAckMetaEnable	in	sl := ' 0 '
dmaWrDescAckMetaAddr	in	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
dmaWrDescAckDropEn	in	sl := ' 0 '
dmaWrDescAckMaxSize	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
dmaWrDescAckContEn	in	sl := ' 0 '
dmaWrDescAckBuffId	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
dmaWrDescAckTimeout	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
dmaWrDescRetValid	out	sl
dmaWrDescRetBuffId	out	slv ( 31 downto 0 )
dmaWrDescRetFirstUser	out	slv ( 7 downto 0 )
dmaWrDescRetLastUser	out	slv ( 7 downto 0 )
dmaWrDescRetSize	out	slv ( 31 downto 0 )
dmaWrDescRetContinue	out	sl
dmaWrDescRetResult	out	slv ( 3 downto 0 )
dmaWrDescRetDest	out	slv ( 7 downto 0 )
dmaWrDescRetId	out	slv ( 7 downto 0 )
dmaWrDescRetAck	in	sl := ' 0 '
dmaWrIdle	out	sl
axiCache	in	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TVALID	in	sl := ' 0 '
M_AXIS_TDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TKEEP	in	slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TLAST	in	sl := ' 0 '
M_AXIS_TDEST	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TID	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TUSER	in	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
M_AXIS_TREADY	out	sl
M_AXI_AWID	out	slv ( 7 downto 0 )
M_AXI_AWADDR	out	slv ( 15 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( 7 downto 0 )
M_AXI_WDATA	out	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M_AXI_WSTRB	out	slv ( DATA_BYTES_G- 1 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( 7 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl
axiWriteCtrlPause	in	sl := ' 0 '
axiWriteCtrlOver	in	sl := ' 0 '

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd