AxiStreamDmaV2DescIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamDmaV2DescIpIntegrator::rtl

Constants
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 8 , ID_BITS_C = > 8 , LEN_BITS_C = > 8 )

Signals
axiResetN	sl := ' 1 '
mAxiAwLock	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
onlineVec	slv ( 0 downto 0 )
acknowledgeVec	slv ( 0 downto 0 )
dmaWrDescReq	AxiWriteDmaDescReqArray ( 0 downto 0 )
dmaWrDescAck	AxiWriteDmaDescAckArray ( 0 downto 0 )
dmaWrDescRet	AxiWriteDmaDescRetArray ( 0 downto 0 )
dmaWrDescRetAckVec	slv ( 0 downto 0 )
dmaRdDescReq	AxiReadDmaDescReqArray ( 0 downto 0 )
dmaRdDescAckVec	slv ( 0 downto 0 )
dmaRdDescRet	AxiReadDmaDescRetArray ( 0 downto 0 )
dmaRdDescRetAckVec	slv ( 0 downto 0 )
axiWriteMasters	AxiWriteMasterArray ( 0 downto 0 )
axiWriteSlaves	AxiWriteSlaveArray ( 0 downto 0 )

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_m_axi	MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut	AxiStreamDmaV2Desc <Entity AxiStreamDmaV2Desc>

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd