AxiStreamDmaV2DescIpIntegrator Entity Reference

Inheritance diagram for AxiStreamDmaV2DescIpIntegrator:

Collaboration diagram for AxiStreamDmaV2DescIpIntegrator:

Entities
AxiStreamDmaV2DescIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns

Ports
axiClk	in	sl
axiRst	in	sl
interrupt	out	sl
online	out	sl
acknowledge	out	sl
axiRdCache	out	slv ( 3 downto 0 )
axiWrCache	out	slv ( 3 downto 0 )
buffGrpPause	out	slv ( 7 downto 0 )
dmaWrDescReqValid	in	sl
dmaWrDescReqId	in	slv ( 7 downto 0 )
dmaWrDescReqDest	in	slv ( 7 downto 0 )
dmaWrDescAckValid	out	sl
dmaWrDescAckAddress	out	slv ( 63 downto 0 )
dmaWrDescAckMetaEnable	out	sl
dmaWrDescAckMetaAddr	out	slv ( 63 downto 0 )
dmaWrDescAckDropEn	out	sl
dmaWrDescAckMaxSize	out	slv ( 31 downto 0 )
dmaWrDescAckContEn	out	sl
dmaWrDescAckBuffId	out	slv ( 31 downto 0 )
dmaWrDescAckTimeout	out	slv ( 31 downto 0 )
dmaWrDescRetValid	in	sl
dmaWrDescRetBuffId	in	slv ( 31 downto 0 )
dmaWrDescRetFirstUser	in	slv ( 7 downto 0 )
dmaWrDescRetLastUser	in	slv ( 7 downto 0 )
dmaWrDescRetSize	in	slv ( 31 downto 0 )
dmaWrDescRetContinue	in	sl
dmaWrDescRetResult	in	slv ( 3 downto 0 )
dmaWrDescRetDest	in	slv ( 7 downto 0 )
dmaWrDescRetId	in	slv ( 7 downto 0 )
dmaWrDescRetAck	out	sl
dmaRdDescReqValid	out	sl
dmaRdDescReqAddress	out	slv ( 63 downto 0 )
dmaRdDescReqBuffId	out	slv ( 31 downto 0 )
dmaRdDescReqFirstUser	out	slv ( 7 downto 0 )
dmaRdDescReqLastUser	out	slv ( 7 downto 0 )
dmaRdDescReqSize	out	slv ( 31 downto 0 )
dmaRdDescReqContinue	out	sl
dmaRdDescReqId	out	slv ( 7 downto 0 )
dmaRdDescReqDest	out	slv ( 7 downto 0 )
dmaRdDescAck	in	sl
dmaRdDescRetValid	in	sl
dmaRdDescRetBuffId	in	slv ( 31 downto 0 )
dmaRdDescRetResult	in	slv ( 2 downto 0 )
dmaRdDescRetAck	out	sl
S_AXI_AWADDR	in	slv ( 11 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 11 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
M_AXI_AWID	out	slv ( 7 downto 0 )
M_AXI_AWADDR	out	slv ( 15 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( 7 downto 0 )
M_AXI_WDATA	out	slv ( 127 downto 0 )
M_AXI_WSTRB	out	slv ( 15 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( 7 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd