AxiStreamDeMuxIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamDeMuxIpIntegrator::rtl

Constants
TDEST_ROUTES_C	Slv8Array ( 1 downto 0 ) := ( 0 = > toSlv ( TDEST_ROUTE_0_G , 8 ) , 1 = > toSlv ( TDEST_ROUTE_1_G , 8 ) )

Signals
axisAResetN	sl := ' 1 '
dynamicRouteMasks	Slv8Array ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
dynamicRouteDests	Slv8Array ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMasters	AxiStreamMasterArray ( 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
mAxisSlaves	AxiStreamSlaveArray ( 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster0	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_shimlayermaster1	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamDeMux <Entity AxiStreamDeMux>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd