AxiStreamCombinerIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamCombinerIpIntegrator::rtl

Constants
SLAVE_AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > DATA_BYTES_G , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > TUSER_WIDTH_G , TUSER_MODE_C = > TUSER_NORMAL_C )
MASTER_AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > DATA_BYTES_G* 2 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > TUSER_WIDTH_G , TUSER_MODE_C = > TUSER_NORMAL_C )

Signals
axisAResetN	sl := ' 1 '
sAxisMasters	AxiStreamMasterArray ( 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
sAxisSlaves	AxiStreamSlaveArray ( 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayerslave0	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayerslave1	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamCombiner <Entity AxiStreamCombiner>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd