AxiStreamCombiner Entity Reference

Entities
AxiStreamCombiner.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
LANES_G	positive := 4
SLAVE_AXI_CONFIG_G	AxiStreamConfigType
MASTER_AXI_CONFIG_G	AxiStreamConfigType

Ports
axisClk	in	sl
axisRst	in	sl
sAxisMasters	in	AxiStreamMasterArray ( LANES_G- 1 downto 0 )
sAxisSlaves	out	AxiStreamSlaveArray ( LANES_G- 1 downto 0 )
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamCombiner.vhd
• build/SRC_VHDL/surf/AxiStreamCombiner.vhd