AxiStreamCombiner.rtl Architecture Reference

Architecture >> AxiStreamCombiner::rtl

Processes
comb	( axisRst , mAxisSlave , r , sAxisMasters )
seq	( axisClk , axisRst )
comb	( axisRst , mAxisSlave , r , sAxisMasters )
seq	( axisClk , axisRst )

Constants
SEQ_C	slv ( 15 downto 8 ) := x " 55 "
REG_INIT_C	RegType := ( master = > axiStreamMasterInit ( MASTER_AXI_CONFIG_G ) , state = > SOF_S , sof = > ' 0 ' , first = > ( others = > ' 1 ' ) , discard = > ( others = > ' 0 ' ) , slaves = > ( others = > AXI_STREAM_SLAVE_INIT_C ) )

Types
FrameState	( SOF_S , EOF_S , ERR_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamCombiner.vhd
• build/SRC_VHDL/surf/AxiStreamCombiner.vhd