Architecture >> AxiStreamBatcherEventBuilder::rtl

Processes
TDEST_REMAP	( sAxisMasters )
comb	( axilReadMaster , axilWriteMaster , axisRst , batcherIdle , blowoffExt , r , rxMasters , timeoutEvent , txSlave )
seq	( axisClk )

Constants
DEST_SIZE_C	integer := bitSize ( NUM_SLAVES_G- 1 )
REG_INIT_C	RegType := ( softRst = > ' 0 ' , hardRst = > ' 0 ' , blowoffReg = > ' 0 ' , blowoff = > ' 0 ' , timerRst = > ' 0 ' , cntRst = > ' 0 ' , ready = > ' 0 ' , maxSubFrames = > toSlv ( NUM_SLAVES_G , 16 ) , timer = > ( others = > ' 0 ' ) , timeout = > ( others = > ' 0 ' ) , bypass = > ( others = > ' 0 ' ) , dataCnt = > ( others = > ( others = > ' 0 ' ) ) , nullCnt = > ( others = > ( others = > ' 0 ' ) ) , transCnt = > ( others = > ' 0 ' ) , timeoutDropCnt = > ( others = > ( others = > ' 0 ' ) ) , accept = > ( others = > ' 0 ' ) , nullDet = > ( others = > ' 0 ' ) , transDet = > ( others = > ' 0 ' ) , timeoutDet = > ( others = > ' 0 ' ) , index = > 0 , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , rxSlaves = > ( others = > AXI_STREAM_SLAVE_INIT_C ) , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
sAxisMastersTmp	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
rxMasters	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
rxSlaves	AxiStreamSlaveArray ( NUM_SLAVES_G- 1 downto 0 )
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType
batcherIdle	sl
timeoutEvent	sl
axisReset	sl

Records
RegType

Instantiations
u_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_dspcomparator	DspComparator <Entity DspComparator>
u_axistreambatcher	AxiStreamBatcher <Entity AxiStreamBatcher>

The documentation for this design unit was generated from the following file:

Processes

Constants