AxiStreamBatcher Entity Reference

Inheritance diagram for AxiStreamBatcher:

Collaboration diagram for AxiStreamBatcher:

Entities
AxiStreamBatcher.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
MAX_NUMBER_SUB_FRAMES_G	positive := 32
SUPER_FRAME_BYTE_THRESHOLD_G	natural := 8192
MAX_CLK_GAP_G	natural := 256
AXIS_CONFIG_G	AxiStreamConfigType
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 1

Ports
axisClk	in	sl
axisRst	in	sl
forceTerm	in	sl := ' 0 '
superFrameByteThreshold	in	slv ( 31 downto 0 ) := toSlv ( SUPER_FRAME_BYTE_THRESHOLD_G , 32 )
maxSubFrames	in	slv ( 15 downto 0 ) := toSlv ( MAX_NUMBER_SUB_FRAMES_G , 16 )
maxClkGap	in	slv ( 31 downto 0 ) := toSlv ( MAX_CLK_GAP_G , 32 )
idle	out	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBatcher.vhd
• protocols/batcher/rtl/AxiStreamBatcher.vhd