AxiStreamBatcherEventBuilder Entity Reference

Inheritance diagram for AxiStreamBatcherEventBuilder:

Collaboration diagram for AxiStreamBatcherEventBuilder:

Entities
AxiStreamBatcherEventBuilder.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
NUM_SLAVES_G	positive := 2
MODE_G	string := " INDEXED "
TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TDEST_LOW_G	integer range 0 to 7 := 0
TRANS_TDEST_G	slv ( 7 downto 0 ) := x " FF "
AXIS_CONFIG_G	AxiStreamConfigType
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
blowoffExt	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
sAxisMasters	in	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
sAxisSlaves	out	AxiStreamSlaveArray ( NUM_SLAVES_G- 1 downto 0 )
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBatcherEventBuilder.vhd
• protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd