AxiStreamBatcherAxil.rtl Architecture Reference

Architecture >> AxiStreamBatcherAxil::rtl

Processes
comb	( axisRst , batcherIdle , r , sAxisSlaveTmp , syncAxilReadMaster , syncAxilWriteMaster )
seq	( axisClk )
comb	( axisRst , batcherIdle , r , sAxisSlaveTmp , syncAxilReadMaster , syncAxilWriteMaster )
seq	( axisClk )

Constants
REG_INIT_C	RegType := ( softRst = > ' 0 ' , blowoff = > ' 0 ' , superFrameByteThreshold = > toSlv ( SUPER_FRAME_BYTE_THRESHOLD_G , 32 ) , maxSubFrames = > toSlv ( MAX_NUMBER_SUB_FRAMES_G , 16 ) , maxClkGap = > toSlv ( MAX_CLK_GAP_G , 32 ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
syncAxilReadMaster	AxiLiteReadMasterType
syncAxilReadSlave	AxiLiteReadSlaveType
syncAxilWriteMaster	AxiLiteWriteMasterType
syncAxilWriteSlave	AxiLiteWriteSlaveType
axisReset	sl
batcherIdle	sl
sAxisSlaveTmp	AxiStreamSlaveType

Records
RegType

Instantiations
u_axistreambatcher	AxiStreamBatcher <Entity AxiStreamBatcher>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_axistreambatcher	AxiStreamBatcher <Entity AxiStreamBatcher>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBatcherAxil.vhd
• protocols/batcher/rtl/AxiStreamBatcherAxil.vhd