AxiStreamBatcherAxil Entity Reference

Inheritance diagram for AxiStreamBatcherAxil:

Collaboration diagram for AxiStreamBatcherAxil:

Entities
AxiStreamBatcherAxil.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLOCK_G	boolean := false
MAX_NUMBER_SUB_FRAMES_G	positive := 32
SUPER_FRAME_BYTE_THRESHOLD_G	natural := 8192
MAX_CLK_GAP_G	natural := 256
AXIS_CONFIG_G	AxiStreamConfigType
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 1

Ports
axisClk	in	sl
axisRst	in	sl
idle	out	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBatcherAxil.vhd
• protocols/batcher/rtl/AxiStreamBatcherAxil.vhd