Architecture >> AxiStreamBatcherAxilWrapper::rtl

Processes
comb	( M_AXIS_TREADY , S_AXIS_TDATA , S_AXIS_TDEST , S_AXIS_TID , S_AXIS_TKEEP , S_AXIS_TLAST , S_AXIS_TUSER , S_AXIS_TVALID , mAxisMaster , sAxisSlave )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > DATA_BYTES_G , TDEST_BITS_C = > 8 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )

Signals
axilHostClk	sl
axilHostRst	sl
axilRstN	sl
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamBatcherAxil <Entity AxiStreamBatcherAxil>

The documentation for this design unit was generated from the following file:

Processes

Constants