SURF
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AxiStreamBatcherAxilWrapper Entity Reference
+ Inheritance diagram for AxiStreamBatcherAxilWrapper:
+ Collaboration diagram for AxiStreamBatcherAxilWrapper:

Entities

AxiStreamBatcherAxilWrapper.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

TPD_G  time := 1 ns
VERSION_G  positive range 1 to 2 := 2
DATA_BYTES_G  positive range 2 to 8 := 8
MAX_NUMBER_SUB_FRAMES_G  positive := 32
SUPER_FRAME_BYTE_THRESHOLD_G  natural := 8192
MAX_CLK_GAP_G  natural := 256
COMMON_CLOCK_G  boolean := true
INPUT_PIPE_STAGES_G  natural := 0
OUTPUT_PIPE_STAGES_G  natural := 1
AXIL_ADDR_WIDTH_G  positive := 12

Ports

axisClk   in   sl
axisRst   in   sl
axilClkIn   in   sl := ' 0 '
axilRstIn   in   sl := ' 1 '
idle   out   sl
S_AXIS_TVALID   in   sl
S_AXIS_TDATA   in   slv ( 8 * DATA_BYTES_G- 1 downto 0 )
S_AXIS_TKEEP   in   slv ( DATA_BYTES_G- 1 downto 0 )
S_AXIS_TLAST   in   sl
S_AXIS_TDEST   in   slv ( 7 downto 0 )
S_AXIS_TID   in   slv ( 7 downto 0 )
S_AXIS_TUSER   in   slv ( 8 * DATA_BYTES_G- 1 downto 0 )
S_AXIS_TREADY   out   sl
M_AXIS_TVALID   out   sl
M_AXIS_TDATA   out   slv ( 8 * DATA_BYTES_G- 1 downto 0 )
M_AXIS_TKEEP   out   slv ( DATA_BYTES_G- 1 downto 0 )
M_AXIS_TLAST   out   sl
M_AXIS_TDEST   out   slv ( 7 downto 0 )
M_AXIS_TID   out   slv ( 7 downto 0 )
M_AXIS_TUSER   out   slv ( 8 * DATA_BYTES_G- 1 downto 0 )
M_AXIS_TREADY   in   sl
S_AXI_AWADDR   in   slv ( AXIL_ADDR_WIDTH_G- 1 downto 0 )
S_AXI_AWPROT   in   slv ( 2 downto 0 )
S_AXI_AWVALID   in   sl
S_AXI_AWREADY   out   sl
S_AXI_WDATA   in   slv ( 31 downto 0 )
S_AXI_WSTRB   in   slv ( 3 downto 0 )
S_AXI_WVALID   in   sl
S_AXI_WREADY   out   sl
S_AXI_BRESP   out   slv ( 1 downto 0 )
S_AXI_BVALID   out   sl
S_AXI_BREADY   in   sl
S_AXI_ARADDR   in   slv ( AXIL_ADDR_WIDTH_G- 1 downto 0 )
S_AXI_ARPROT   in   slv ( 2 downto 0 )
S_AXI_ARVALID   in   sl
S_AXI_ARREADY   out   sl
S_AXI_RDATA   out   slv ( 31 downto 0 )
S_AXI_RRESP   out   slv ( 1 downto 0 )
S_AXI_RVALID   out   sl
S_AXI_RREADY   in   sl

The documentation for this design unit was generated from the following file: