Architecture >> AxiRingBufferTb::testbed

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := CLK_PERIOD_C/ 4
DATA_BYTES_C	positive := 4
BURST_BYTES_C	positive := 256
RING_BUFF_ADDR_WIDTH_C	positive := 10
DATA_BITSIZE_C	positive := log2 ( DATA_BYTES_C )
MEM_BITSIZE_C	positive := RING_BUFF_ADDR_WIDTH_C+ DATA_BITSIZE_C
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > DATA_BYTES_C , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 0 , tUserBits = > 2 , tIdBits = > 0 )
AXI_CONFIG_C	AxiConfigType := ( ADDR_WIDTH_C = > MEM_BITSIZE_C , DATA_BYTES_C = > DATA_BYTES_C , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )
TRIG_INDEX_C	positive := 2100
REG_INIT_C	RegType := ( passed = > ' 0 ' , failed = > ' 0 ' , extTrig = > ' 0 ' , dataValue = > ( others = > ' 0 ' ) , expectedValue = > toSlv ( TRIG_INDEX_C- 959 , 32 ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 1 '
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
axisMaster	AxiStreamMasterType
passed	sl := ' 0 '
failed	sl := ' 0 '

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_mem	AxiRam <Entity AxiRam>
u_dut	AxiRingBuffer <Entity AxiRingBuffer>
u_clkrst	ClkRst <Entity ClkRst>
u_mem	AxiRam <Entity AxiRam>
u_dut	AxiRingBuffer <Entity AxiRingBuffer>

The documentation for this design unit was generated from the following files:

Processes

Constants