AxiRingBufferIpIntegrator.rtl Architecture Reference

Architecture >> AxiRingBufferIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 4 , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 8 , tUserBits = > 2 , tIdBits = > 0 )

Signals
axisResetN	sl := ' 1 '
axiResetN	sl := ' 1 '
axisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C

Instantiations
u_axis	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_axi	MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut	AxiRingBuffer <Entity AxiRingBuffer>

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The documentation for this design unit was generated from the following file:

• axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd