AxiRingBufferIpIntegrator Entity Reference

Inheritance diagram for AxiRingBufferIpIntegrator:

Collaboration diagram for AxiRingBufferIpIntegrator:

Entities
AxiRingBufferIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Ports
dataClk	in	sl
dataRst	in	sl
dataValid	in	sl
dataValue	in	slv ( 31 downto 0 )
extTrig	in	sl
axisClk	in	sl
axisRst	in	sl
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( 31 downto 0 )
M_AXIS_TKEEP	out	slv ( 3 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 7 downto 0 )
M_AXIS_TID	out	slv ( 0 downto 0 )
M_AXIS_TUSER	out	slv ( 1 downto 0 )
M_AXIS_TREADY	in	sl
axiClk	in	sl
axiRst	in	sl
M_AXI_AWID	out	slv ( 0 downto 0 )
M_AXI_AWADDR	out	slv ( 15 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( 0 downto 0 )
M_AXI_WDATA	out	slv ( 31 downto 0 )
M_AXI_WSTRB	out	slv ( 3 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( 0 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl
M_AXI_ARID	out	slv ( 0 downto 0 )
M_AXI_ARADDR	out	slv ( 15 downto 0 )
M_AXI_ARLEN	out	slv ( 7 downto 0 )
M_AXI_ARSIZE	out	slv ( 2 downto 0 )
M_AXI_ARBURST	out	slv ( 1 downto 0 )
M_AXI_ARLOCK	out	sl
M_AXI_ARCACHE	out	slv ( 3 downto 0 )
M_AXI_ARPROT	out	slv ( 2 downto 0 )
M_AXI_ARREGION	out	slv ( 3 downto 0 )
M_AXI_ARQOS	out	slv ( 3 downto 0 )
M_AXI_ARVALID	out	sl
M_AXI_ARREADY	in	sl
M_AXI_RID	in	slv ( 0 downto 0 )
M_AXI_RDATA	in	slv ( 31 downto 0 )
M_AXI_RRESP	in	slv ( 1 downto 0 )
M_AXI_RLAST	in	sl
M_AXI_RVALID	in	sl
M_AXI_RREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd