AxiRateGenIpIntegrator.rtl Architecture Reference

Architecture >> AxiRateGenIpIntegrator::rtl

Constants
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > AXI_ADDR_WIDTH_G , DATA_BYTES_C = > AXI_DATA_WIDTH_G/ 8 , ID_BITS_C = > AXI_ID_WIDTH_G , LEN_BITS_C = > 8 )

Signals
axiResetN	sl := ' 1 '
axilResetN	sl := ' 1 '
mAxiAwLock	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
mAxiArLock	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C

Instantiations
u_s_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_m_axi	MasterAxiIpIntegrator <Entity MasterAxiIpIntegrator>
u_dut	AxiRateGen <Entity AxiRateGen>

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The documentation for this design unit was generated from the following file:

• axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd