AxiRateGen Entity Reference

Inheritance diagram for AxiRateGen:

Collaboration diagram for AxiRateGen:

Entities
AxiRateGen.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
AXI_CONFIG_G	AxiConfigType

Ports
axiClk	in	sl
axiRst	in	sl
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType
axilClk	in	sl
axilRst	in	sl
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiRateGen.vhd
• build/SRC_VHDL/surf/AxiRateGen.vhd