AxiRateGen.rtl Architecture Reference

Architecture >> AxiRateGen::rtl

Processes
comb	( axiReadSlave , axiRst , axiWriteSlave , axilReadMaster , axilWriteMaster , r )
seq	( axiClk )
comb	( axiReadSlave , axiRst , axiWriteSlave , axilReadMaster , axilWriteMaster , r )
seq	( axiClk )

Constants

REG_INIT_C

RegType := ( wrState = > WRITE_ADDR_S , rdState = > READ_ADDR_S , awlen = > x " 00 " , writeSize = > x " FFF " , wrTimer = > x " 0000_0000 " , rdTimer = > x " 0000_0000 " , wrEnable = > ' 0 ' , rdEnable = > ' 0 ' , wrSize = > x " FFF " , rdSize = > x " FFF " , wrPeriod = > x " 0000_FFFF " , rdPeriod = > x " 0000_FFFF " , awburst = > " 01 " , awcache = > " 1111 " , arburst = > " 01 " , arcache = > " 1111 " , axiWriteMaster = > axiWriteMasterInit ( AXI_CONFIG_G ) , axiReadMaster = > axiReadMasterInit ( AXI_CONFIG_G ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
WrStateType	( WRITE_ADDR_S , WRITE_DATA_S , WRITE_RESP_S )
RdStateType	( READ_ADDR_S , READ_DATA_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType

Records
RegType

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiRateGen.vhd
• build/SRC_VHDL/surf/AxiRateGen.vhd