AxiRateGenIpIntegrator Entity Reference

Inheritance diagram for AxiRateGenIpIntegrator:

Collaboration diagram for AxiRateGenIpIntegrator:

Entities
AxiRateGenIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := true
AXI_ADDR_WIDTH_G	positive range 12 to 64 := 16
AXI_DATA_WIDTH_G	positive range 32 to 1024 := 32
AXI_ID_WIDTH_G	positive := 4

Ports
axiClk	in	sl
axiRst	in	sl
axilClk	in	sl
axilRst	in	sl
S_AXIL_AWADDR	in	slv ( 7 downto 0 )
S_AXIL_AWPROT	in	slv ( 2 downto 0 )
S_AXIL_AWVALID	in	sl
S_AXIL_AWREADY	out	sl
S_AXIL_WDATA	in	slv ( 31 downto 0 )
S_AXIL_WSTRB	in	slv ( 3 downto 0 )
S_AXIL_WVALID	in	sl
S_AXIL_WREADY	out	sl
S_AXIL_BRESP	out	slv ( 1 downto 0 )
S_AXIL_BVALID	out	sl
S_AXIL_BREADY	in	sl
S_AXIL_ARADDR	in	slv ( 7 downto 0 )
S_AXIL_ARPROT	in	slv ( 2 downto 0 )
S_AXIL_ARVALID	in	sl
S_AXIL_ARREADY	out	sl
S_AXIL_RDATA	out	slv ( 31 downto 0 )
S_AXIL_RRESP	out	slv ( 1 downto 0 )
S_AXIL_RVALID	out	sl
S_AXIL_RREADY	in	sl
M_AXI_AWID	out	slv ( AXI_ID_WIDTH_G- 1 downto 0 )
M_AXI_AWADDR	out	slv ( AXI_ADDR_WIDTH_G- 1 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( AXI_ID_WIDTH_G- 1 downto 0 )
M_AXI_WDATA	out	slv ( AXI_DATA_WIDTH_G- 1 downto 0 )
M_AXI_WSTRB	out	slv ( ( AXI_DATA_WIDTH_G/ 8 ) - 1 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( AXI_ID_WIDTH_G- 1 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl
M_AXI_ARID	out	slv ( AXI_ID_WIDTH_G- 1 downto 0 )
M_AXI_ARADDR	out	slv ( AXI_ADDR_WIDTH_G- 1 downto 0 )
M_AXI_ARLEN	out	slv ( 7 downto 0 )
M_AXI_ARSIZE	out	slv ( 2 downto 0 )
M_AXI_ARBURST	out	slv ( 1 downto 0 )
M_AXI_ARLOCK	out	sl
M_AXI_ARCACHE	out	slv ( 3 downto 0 )
M_AXI_ARPROT	out	slv ( 2 downto 0 )
M_AXI_ARREGION	out	slv ( 3 downto 0 )
M_AXI_ARQOS	out	slv ( 3 downto 0 )
M_AXI_ARVALID	out	sl
M_AXI_ARREADY	in	sl
M_AXI_RID	in	slv ( AXI_ID_WIDTH_G- 1 downto 0 )
M_AXI_RDATA	in	slv ( AXI_DATA_WIDTH_G- 1 downto 0 )
M_AXI_RRESP	in	slv ( 1 downto 0 )
M_AXI_RLAST	in	sl
M_AXI_RVALID	in	sl
M_AXI_RREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd