AxiRamTb.testbed Architecture Reference

Architecture >> AxiRamTb::testbed

Processes
PROCESS_16	( clk )
PROCESS_75	( clk )

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := CLK_PERIOD_C/ 4
AXI_CONFIG_C	AxiConfigType := ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 8 , ID_BITS_C = > 4 , LEN_BITS_C = > 8 )
START_ADDR_C	slv ( AXI_CONFIG_C.ADDR_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
STOP_ADDR_C	slv ( AXI_CONFIG_C.ADDR_WIDTH_C- 1 downto 0 ) := ( others = > ' 1 ' )

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
rstL	sl := ' 1 '
memReady	sl := ' 0 '
memError	sl := ' 0 '
passed	sl := ' 0 '
failed	sl := ' 0 '
axiWriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_mem	AxiRam <Entity AxiRam>
u_aximemtester	AxiMemTester <Entity AxiMemTester>
u_clkrst	ClkRst <Entity ClkRst>
u_mem	AxiRam <Entity AxiRam>
u_aximemtester	AxiMemTester <Entity AxiMemTester>

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The documentation for this design unit was generated from the following files:

• axi/axi4/tb/AxiRamTb.vhd
• build/SRC_VHDL/surf/AxiRamTb.vhd