AxiMemTester Entity Reference

Inheritance diagram for AxiMemTester:

Collaboration diagram for AxiMemTester:

Entities
AxiMemTester.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
START_ADDR_G	slv := X " 00000000 "
STOP_ADDR_G	slv := X " FFFFFFFF "
BURST_LEN_G	positive range 1 to 4096 := 4096
AXI_CONFIG_G	AxiConfigType

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
memReady	out	sl
memError	out	sl
axiClk	in	sl
axiRst	in	sl
start	in	sl
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiMemTester.vhd
• build/SRC_VHDL/surf/AxiMemTester.vhd