AxiMemTester.rtl Architecture Reference

Architecture >> AxiMemTester::rtl

Functions
slv	genSeed
slv	genSeed

Processes
comb	( axiReadSlave , axiRst , axiWriteSlave , r , start )
seq	( axiClk )
combLite	( axilReadMaster , axilRst , axilWriteMaster , busy , done , error , rDataOut , rErrData , rErrResp , rLite , rPatternOut , rTimer , startSync , wErrResp , wTimer )
seqLite	( axilClk )
comb	( axiReadSlave , axiRst , axiWriteSlave , r , start )
seq	( axiClk )
combLite	( axilReadMaster , axilRst , axilWriteMaster , busy , done , error , rDataOut , rErrData , rErrResp , rLite , rPatternOut , rTimer , startSync , wErrResp , wTimer )
seqLite	( axilClk )

Constants
START_C	slv ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 ) := START_ADDR_G ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 )
START_ADDR_C	slv ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 ) := START_C ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 12 ) & x " 000 "
STOP_C	slv ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 ) := STOP_ADDR_G ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 )
STOP_ADDR_C	slv ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 0 ) := STOP_C ( AXI_CONFIG_G.ADDR_WIDTH_C- 1 downto 12 ) & x " 000 "
DATA_BITS_C	natural := 8 * AXI_CONFIG_G.DATA_BYTES_C
AXI_LEN_C	slv ( 7 downto 0 ) := getAxiLen ( AXI_CONFIG_G , BURST_LEN_G )
PRBS_TAPS_C	NaturalArray := ( 0 = > ( DATA_BITS_C- 1 ) , 1 = > ( DATA_BITS_C/ 2 ) , 2 = > ( DATA_BITS_C/ 4 ) )
DATA_SYNC_BITS_C	natural := ite ( DATA_BITS_C< 1024 , DATA_BITS_C , 1024 )
PRBS_SEED_C	slv ( DATA_BITS_C- 1 downto 0 ) := genSeed
REG_INIT_C	RegType := ( busy = > ' 0 ' , done = > ' 0 ' , error = > ' 0 ' , wErrResp = > ' 0 ' , rErrResp = > ' 0 ' , rErrData = > ' 0 ' , wTimerEn = > ' 0 ' , rTimerEn = > ' 0 ' , wTimer = > ( others = > ' 0 ' ) , rTimer = > ( others = > ' 0 ' ) , len = > AXI_LEN_C , address = > ( others = > ' 0 ' ) , randomData = > PRBS_SEED_C , rData = > ( others = > ' 0 ' ) , rPattern = > ( others = > ' 0 ' ) , state = > IDLE_S , axiWriteMaster = > AXI_WRITE_MASTER_INIT_C , axiReadMaster = > AXI_READ_MASTER_INIT_C )
REG_LITE_INIT_C	RegLiteType := ( memReady = > ' 0 ' , memError = > ' 0 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , WRITE_ADDR_S , WRITE_DATA_S , WRITE_RESP_S , READ_ADDR_S , READ_DATA_S , DONE_S , ERROR_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
startSync	sl
busy	sl
done	sl
error	sl
wTimer	slv ( 31 downto 0 )
rTimer	slv ( 31 downto 0 )
wErrResp	sl
rErrResp	sl
rErrData	sl
rDataIn	slv ( DATA_SYNC_BITS_C- 1 downto 0 )
rPatternIn	slv ( DATA_SYNC_BITS_C- 1 downto 0 )
rDataOut	slv ( 1023 downto 0 )
rPatternOut	slv ( 1023 downto 0 )
rLite	RegLiteType := REG_LITE_INIT_C
rinLite	RegLiteType

Records
RegType
RegLiteType

Instantiations
u_syncbits	SynchronizerVector <Entity SynchronizerVector>
u_wtimer	SynchronizerFifo <Entity SynchronizerFifo>
u_rtimer	SynchronizerFifo <Entity SynchronizerFifo>
u_rdata	SynchronizerVector <Entity SynchronizerVector>
u_rpattern	SynchronizerVector <Entity SynchronizerVector>
u_syncbits	SynchronizerVector <Entity SynchronizerVector>
u_wtimer	SynchronizerFifo <Entity SynchronizerFifo>
u_rtimer	SynchronizerFifo <Entity SynchronizerFifo>
u_rdata	SynchronizerVector <Entity SynchronizerVector>
u_rpattern	SynchronizerVector <Entity SynchronizerVector>

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiMemTester.vhd
• build/SRC_VHDL/surf/AxiMemTester.vhd