AxiMonAxiLIpIntegrator.rtl Architecture Reference

Architecture >> AxiMonAxiLIpIntegrator::rtl

Constants
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 4 , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )

Signals
axilResetN	sl := ' 1 '
axiWriteMasters	AxiWriteMasterArray ( 0 downto 0 ) := ( others = > AXI_WRITE_MASTER_INIT_C )
axiWriteSlaves	AxiWriteSlaveArray ( 0 downto 0 ) := ( others = > AXI_WRITE_SLAVE_INIT_C )
axiReadMasters	AxiReadMasterArray ( 0 downto 0 ) := ( others = > AXI_READ_MASTER_INIT_C )
axiReadSlaves	AxiReadSlaveArray ( 0 downto 0 ) := ( others = > AXI_READ_SLAVE_INIT_C )
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiMonAxiL <Entity AxiMonAxiL>

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The documentation for this design unit was generated from the following file:

• axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd